Senior FPGA Design Engineer
Remote
The future of aerospace and defense starts here.
Ursa Major was founded to revolutionize how America and its allies access and apply high-performance propulsion, from hypersonics to solid rocket motors, satellite maneuvering and launch. We design and deliver propulsion and defense systems that solve the most urgent and critical national security demands.
Our products and technologies require an extraordinary team. A team that will mold tomorrow’s technologies while deploying today’s best. We are an intrinsically motivated team that has a passion for solving problems and empowering each other every day to develop our skills, knowing that there is always room for growth.
As a Senior FPGA Designer you will be an integral part of the Avionics development team. You will architect, develop RTL code, perform simulations, complete synthesis and place and route, run and analyze static timing analyses, generate programming files, prepare and present design review materials and participate in hardware electrical checkout.
Responsibilities:
- Architect and generate ASIC/FPGA RTL code
- Generate test cases and run simulations to verify the functionality of ASIC/FPGA code
- Complete synthesis and resolve all errors/warnings
- Complete place and route and ensure sufficient timing margin through STA
- Generate programming files
- Test hardware as part of post-silicon validation or integrated test environment (Hardware in the Loop)
- Help debug ASIC/FPGA designs and/or test issues
- Prepare materials for peer reviews and major program design reviews
Required Qualifications:
- Bachelor’s degree in Electrical or Computer Engineering
- Mastery of a hardware description language such as VHDL, Verilog or SystemVerilog
- Ability to develop a variety of RTL functions including DSP, DAC/ADC interfaces, bus interconnect, control logic, and communication cores.
- Comfortable developing drivers and software applications for RTL functions
- Ability to use Python, TCL, or other high-level languages for simulation, hardware testing and tool development
- Experience with timing closure and safe CDC design in FPGAs
- Experience with Xilinx or Microsemi FPGAs
- Experience working with hardware, reading schematics, and using hardware debugging equipment
- Ability to work effectively in teams or individually
- Ability to be self-directed and balance several tasks at one time
Desirable Experience:
- Experience with Python and MATLAB for modeling and code generation
- Experience using Cocotb or other PLI/DPI based co-simulation environment
- Working knowledge of industry standard interfaces such as Ethernet, SpaceWire, and 1553
- Experience developing on a SoC platform such as the Zynq MPSoC Ultrascale or Microsemi Smartfusion2.
- Exposure to fault-tolerant, high-reliability, safety-critical, or radiation-tolerant FPGA development methodologies
- Familiarity with Continuous Integration / Continuous Deployment Tools
- Familiarity with GIT
Colorado law requires us to tell you the base compensation range of this role, which is $135,000 – $155,000, determined by your education, experience, knowledge, skills, and abilities. The salary range for this role is intentionally wide as we are evaluating individuals based on their unique experience and abilities to fit our needs. Most importantly, we are excited to meet you, and see if you are a great fit for our team. What we can’t quantify for you are the exciting challenges, supportive team, and amazing culture we enjoy.
Benefits Include: (Please note, Interns are not eligible for benefits)
- Unlimited PTO – Vacation, Sick, Personal, and Bereavement
- Paid Parental and Adoptive Leave
- Medical, Dental and Vision Insurance
- Tax Advantage Accounts (HSA/FSA)
- Employer Paid Short and Long Term Disability, Basic Life, AD&D
- Additional Benefit Options Including Voluntary Life and Emergency Medical Transport
- EAP Program
- Retirement Savings Plan – Traditional 401(k) and a Roth 401(k)
- Equity Grants in the Company
How To Apply:
Interested candidates are encouraged to apply by filling out the application below and clicking “Submit Application”. This position will be posted for a minimum of 3 days and will remain open until filled or adjusted based on the volume of applicants.